Analytical Evaluation on Hysteresis Performance of Circular Shear Panel Damper

The idea of adding metallic energy dissipaters to a structure to absorb a large part of the seismic energy began four decades ago. There are several types of metal-based devices conceived as dampers for the seismic energy absorber whereby damages to the major structural components could be minimized for both new and existing structures. This paper aimed to develop and evaluate structural performance of both stiffened and non stiffened circular shear panel damper for passive seismic energy protection by inelastic deformation. Structural evaluation was done using commercially available nonlinear FE simulation program. Diameter-to-thickness ratio is employed as main parameter to investigate the hysteresis performance of stiffened and unstiffened circular shear panel. Depending on these parameters three different buckling mode and hysteretic behavior was found: yielding prior to buckling without strength degradation, yielding prior to buckling with strength degradation and yielding with buckling and strength degradation which forms pinching at initial displacement. Hence, the hysteresis behavior is identified, specimens which deform without strength degradation so it will be used as passive energy dissipating device in civil engineering structures

Analytical Evaluation on Hysteresis Performance of Circular Shear Panel Damper

The idea of adding metallic energy dissipaters to a structure to absorb a large part of the seismic energy began four decades ago. There are several types of metal-based devices conceived as dampers for the seismic energy absorber whereby damages to the major structural components could be minimized for both new and existing structures. This paper aimed to develop and evaluate structural performance of both stiffened and non stiffened circular shear panel damper for passive seismic energy protection by inelastic deformation. Structural evaluation was done using commercially available nonlinear FE simulation program. Diameter-to-thickness ratio is employed as main parameter to investigate the hysteresis performance of stiffened and unstiffened circular shear panel. Depending on these parameters three different buckling mode and hysteretic behavior was found: yielding prior to buckling without strength degradation, yielding prior to buckling with strength degradation and yielding with buckling and strength degradation which forms pinching at initial displacement. Hence, the hysteresis behavior is identified, specimens which deform without strength degradation so it will be used as passive energy dissipating device in civil engineering structures

Analytical Evaluation on Hysteresis Performance of Circular Shear Panel Damper

The idea of adding metallic energy dissipaters to a structure to absorb a large part of the seismic energy began four decades ago. There are several types of metal-based devices conceived as dampers for the seismic energy absorber whereby damages to the major structural components could be minimized for both new and existing structures. This paper aimed to develop and evaluate structural performance of both stiffened and non stiffened circular shear panel damper for passive seismic energy protection by inelastic deformation. Structural evaluation was done using commercially available nonlinear FE simulation program. Diameter-to-thickness ratio is employed as main parameter to investigate the hysteresis performance of stiffened and unstiffened circular shear panel. Depending on these parameters three different buckling mode and hysteretic behavior was found: yielding prior to buckling without strength degradation, yielding prior to buckling with strength degradation and yielding with buckling and strength degradation which forms pinching at initial displacement. Hence, the hysteresis behavior is identified, specimens which deform without strength degradation so it will be used as passive energy dissipating device in civil engineering structures

Analytical Evaluation on Hysteresis Performance of Circular Shear Panel Damper

The idea of adding metallic energy dissipaters to a structure to absorb a large part of the seismic energy began four decades ago. There are several types of metal-based devices conceived as dampers for the seismic energy absorber whereby damages to the major structural components could be minimized for both new and existing structures. This paper aimed to develop and evaluate structural performance of both stiffened and non stiffened circular shear panel damper for passive seismic energy protection by inelastic deformation. Structural evaluation was done using commercially available nonlinear FE simulation program. Diameter-to-thickness ratio is employed as main parameter to investigate the hysteresis performance of stiffened and unstiffened circular shear panel. Depending on these parameters three different buckling mode and hysteretic behavior was found: yielding prior to buckling without strength degradation, yielding prior to buckling with strength degradation and yielding with buckling and strength degradation which forms pinching at initial displacement. Hence, the hysteresis behavior is identified, specimens which deform without strength degradation so it will be used as passive energy dissipating device in civil engineering structures

Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.PhDCommittee Chair: Tentzeris, Manos M.; Committee Member: Kang, Sung Ha; Committee Member: Kim, Jongman; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saiba

10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector

An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an ILCM has a critical problem in that its jitter performance is sensitive to process, voltage, and temperature (PVT) variations. Thus, in general, an ILCM must be equipped with a dedicated PVT-calibrator to mitigate the sensitivity of its performance to PVT variations. One of the most general calibration methods is to use a phase-locked loop (PLL). This method can correct static frequency deviations of a voltage-controlled oscillator (VCO) due to process variations, but it cannot prevent real-time frequency drifts due to temperature or voltage variations [1]. Recently, many efforts have been made to develop new PVT-calibrators, capable of continuous frequency tracking [1-6]. In [1-3], frequency drifts were monitored by a replica-VCO or a delay-locked loop (DLL) that used the same delay cells as the main VCO. However, in these architectures, each calibrator must spend the same amount of the power as the VCO. In addition, mismatches between delay cells limit the calibrating precision or demand an additional calibrating step. References [4-6] presented frequency-tracking loops (FTLs) based on various methods to detect the phase shifts of VCO outputs when reference-pulses are injected. Reference [4] used a time-to-digital converter (TDC) to detect the phase shifts, but it had large power consumption and silicon area due to the many digital circuits. Although the FTL of [5] used a timing-adjusted phase detector (PD), it could suffer from large in-band noise or spurs since the switches of the charge pump (CP) must be on for a considerable duration in every period. In [6], a pulse-gating technique that periodically skipped the injection was presented, but it could generate fractional spurs

A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells

This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than ?? 4%

An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals

This letter presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65-nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2 . At a 3.12-GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB.close

Analytical Evaluation on Hysteresis Performance of Circular Shear Panel Damper

The idea of adding metallic energy dissipaters to a structure to absorb a large part of the seismic energy began four decades ago. There are several types of metal-based devices conceived as dampers for the seismic energy absorber whereby damages to the major structural components could be minimized for both new and existing structures. This paper aimed to develop and evaluate structural performance of both stiffened and non stiffened circular shear panel damper for passive seismic energy protection by inelastic deformation. Structural evaluation was done using commercially available nonlinear FE simulation program. Diameter-to-thickness ratio is employed as main parameter to investigate the hysteresis performance of stiffened and unstiffened circular shear panel. Depending on these parameters three different buckling mode and hysteretic behavior was found: yielding prior to buckling without strength degradation, yielding prior to buckling with strength degradation and yielding with buckling and strength degradation which forms pinching at initial displacement. Hence, the hysteresis behavior is identified, specimens which deform without strength degradation so it will be used as passive energy dissipating device in civil engineering structures

A Theoretically Sound Approach to Analog Circuit Sizing

We consider the problem of determining the sizes of electrical components in analog circuits, such as operational amplifiers, that maximize a primary performance measure while satisfying some conditions on secondary performance measures. We propose a method that uses a circuit simulator, such as SPICE, to evaluate the performance measures exactly and updates the sizes of the electrical components iteratively using an optimization procedure, which is a variant of the Lagrangian method. The proposed approach guarantees convergence to a local optimal solution under mild conditions. Numerical results demonstrate that the proposed method finds optimal sizes successfully in various circuits including one-stage and two-stage operational amplifiers, a voltage-controlled oscillator, and an inverter chain